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π¦ Description
1) Serial ATA(SATA) host controller chip with 32-bit interfacing
2) Compliant with serial ATA 1.0
3) Supports two independent serial ATA ports with data transfer rate up to 1.5Gb/s
4) Built-in 256 byte FIFO per port for fast read/write operations
5) Supports Microsoft generic IDE operation and intel nus master DMA operations
2) Compliant with serial ATA 1.0
3) Supports two independent serial ATA ports with data transfer rate up to 1.5Gb/s
4) Built-in 256 byte FIFO per port for fast read/write operations
5) Supports Microsoft generic IDE operation and intel nus master DMA operations
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